Semiconductor device and method of manufacturing same, and management system of semiconductor device

ABSTRACT

After stacking m wafers in each of which a plurality of semiconductor chips are formed, the m wafers are diced to semiconductor chips to form a first chip stack having m of the semiconductor chips stacked, and, after stacking n wafers, the n wafers are diced to semiconductor chips to form a second chip stack having n of the semiconductor chips stacked. Next, the first chip stack is sorted according to the number of defective semiconductor chips included in the first chip stack, and the second chip stack is sorted according to the number of defective semiconductor chips included in the second chip stack. Furthermore, the first chip stack or the second chip stack after sorting are combined to form a third chip stack.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is based on and claims the benefit of priority fromprior Japanese Patent Application No. 2011-217929, filed on Sep. 30,2011, the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described in the present specification relate to asemiconductor device and a method of manufacturing the same, and to amanagement system of a semiconductor device.

BACKGROUND

Manufacturing technology in which a stacked plurality of semiconductorchips are connected by a silicon penetrating electrode is attractingattention as a means of achieving an even higher degree of integrationof a semiconductor integrated circuit. Known methods in the case ofstacking a plurality of semiconductor chips include a method that firstperforms dicing of wafers and then stacks the chips (Chip to Chipstacking method, hereafter called “C2C method”), and a method thatstacks the wafers before dicing the wafers and thereby performs dicingafter stacking (Wafer to Wafer method, hereafter called “W2W method”).

The W2W method is superior to the C2C method in terms of manufacturingefficiency, but has a disadvantage that, when defect rate in each of thewafers increases, the defect rate rises cumulatively with increasingnumber of stacked wafers, thereby leading to a fall in product yield andrise in final product cost.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic view showing an overall configuration of asemiconductor device according to the present embodiment.

FIG. 2 shows manufacturing processes of the semiconductor deviceaccording to the present embodiment.

FIG. 3 includes tables showing the relationship between proportion ofdefective semiconductor chips among the semiconductor chips included inone wafer, number of stacked wafers (number stacked), and yield in afirst chip stack 20 or a second chip stack 30.

FIG. 4 shows manufacturing processes of a semiconductor device accordingto an embodiment.

FIG. 5 shows a management system of the semiconductor device accordingto the present embodiment.

DETAILED DESCRIPTION

In a method of manufacturing a semiconductor device in an embodimentdescribed below, first, after stacking m wafers in each of which areformed a plurality of semiconductor chips, dicing of the m wafers isperformed on the basis of the semiconductor chips to form a first chipstack having m of the semiconductor chips stacked, and, after stacking nof the wafers, dicing of the n wafers is performed on the basis of thesemiconductor chips to form a second chip stack having n of thesemiconductor chips stacked. Next, the first chip stack is sortedaccording to the number of defective semiconductor chips included in thefirst chip stack, and the second chip stack is sorted according to thenumber of defective semiconductor chips included in the second chipstack. Furthermore, the first chip stack or the second chip stack aftersorting are combined to form a third chip stack.

Next, a semiconductor device and a method of manufacturing the sameaccording to an embodiment of the present invention are described indetail with reference to the drawings.

A configuration of a semiconductor device 1 according to the presentembodiment is described with reference to FIG. 1. As shown in FIG. 1,the semiconductor device of the present embodiment comprises a thirdchip stack 40 on a package substrate 10, the third chip stack 40 beingconfigured by stacking a first chip stack 20 and a second chip stack 30.The first chip stack 20 and the second chip stack 30 are electricallyconnected by a ball grid array (BGA) 50 or the like.

The first chip stack 20 is formed by stacking m memory chips C2 ₁-C2_(m). The memory chips C2 ₁-C2 _(m) each include a silicon wafer 11 andan element forming layer 12 formed on this silicon wafer 11, and arejoined to one another by an adhesive agent 13. The memory chips C2 ₁-C2_(m) each include a penetrating electrode TSV and are electricallyconnected to separate memory chips C2 provided above and below, by thispenetrating electrode TSV.

Similarly, the second chip stack 30 is formed by stacking n memory chipsC3 ₁-C3 _(n). The memory chips C3 ₁-C3 _(n) each include a penetratingelectrode TSV and are electrically connected to separate memory chips C3provided above and below, by this penetrating electrode TSV.

Note that a distance d between the memory chips C2 in the first chipstack 20 is smaller than a distance D between the memory chip C2 ₁ in alowermost layer of the first chip stack 20 and the memory chip C3 _(n)in an uppermost layer of the second chip stack 30 connected by the BGA50.

The numbers m and n are determined by the number p of non-defectivememory chips C to be included finally in the third chip stack 40.Preferably, n is a number larger than m, for example, a number largerthan m by an amount of 1 (n=m+1).

The third chip stack 40 may include at least one, specifically (m+n−p),defective semiconductor chips. When there is one defective semiconductorchip included in the third chip stack 40, either one of the first chipstack 20 and the second chip stack 30 includes one defectivesemiconductor chip, and the other of the first chip stack 20 and thesecond chip stack 30 does not include a defective semiconductor chip buthas all of the semiconductor chips non-defective. In this specification,the expression “defective semiconductor chip” is used with the meaningthat the chip is defective in its entirety (the chip itself isdefective), and that the chip is not provided for use in its entirety.

The first chip stack 20 and the second chip stack of the presentembodiment are formed using the above-mentioned W2W method. That is,after stacking a plurality of wafers in each of which a plurality ofsemiconductor chips are formed, wafers are diced to semiconductor chipsto form a chip stack having a plurality of the semiconductor chipsstacked. A method of manufacturing the first chip stack 20 and thesecond chip stack 30 by the W2W method herein is described withreference to FIGS. 2A-2I.

First, as shown in FIG. 2A, the element forming layer 12 configured fromsilicon is formed on the silicon wafer 11 by epitaxial growth or thelike. Then, a semiconductor memory is formed on this element forminglayer 12 by a well-known method. The semiconductor memory is, forexample, NAND cell type flash memory, dynamic random access memory(DRAM), static random access memory (SRAM), magnetoresistive memory,resistance varying memory, and so on. That is, types of thesemiconductor memory are not limited to specific ones. A plurality ofmemory chips (for example, about 500) are formed on one silicon wafer11.

Then, as shown in FIG. 2B, after the adhesive agent 13 is coated on anupper surface of the element forming layer 12, a support substrate 14and the element forming layer 12 are adhered by this adhesive agent 13.Employable as the adhesive agent 13 is, for example, an acrylic resin,or the like. Moreover, the support substrate 14 may be formed by, forexample, glass.

Next, as shown in FIG. 2C, chemical mechanical polishing (CMP) or thelike is employed to reduce a film thickness of the silicon wafer 11, andthen, as shown in FIG. 2D, a substrate 15 is attached to an underside ofthe silicon wafer 11 via the adhesive agent 13. Then, as shown in FIG.2E, the support substrate 14 is stripped.

Then, as shown in FIG. 2F, penetrating electrodes TSV are formed in eachof the memory chips so as to penetrate the element forming layer 12 andthe silicon wafer 11. As an example, the penetrating electrodes TSV areformed by the following kind of process. First, photolithography and dryetching are executed to form contact vias in the element forming layer12 and the silicon wafer 11. Then, a CVD method or the like is employedto fill those contact vias with a metal film (tungsten or the like).Then, CMP is executed to remove any of the metal film formed outside thecontact vias, whereby the penetrating electrodes as in FIG. 2F areformed.

Hereafter, as shown in FIG. 2G, by repeating similar processes to thoseshown in FIGS. 2A-2F multiple times and adhering by the adhesive agent13, a plurality of silicon wafers 11 are stacked and attain a state ofbeing electrically connected to one another by the penetratingelectrodes TSV. As a result, the semiconductor memory chips aligned inthe stacking direction formed on a plurality of the silicon wafers 11attain a state of being electrically connected to one another.

Then, as shown in FIG. 2H, a dicing tape 16 is attached to an uppersurface of the element forming layer 12 formed on an uppermost layer ofthe silicon wafers 11. Then, as shown in FIG. 2I, dicing is performedalong dicing lines T formed between the memory chips to cut the stackedwafers into memory chip units. This allows the first chip stack 20 asshown in FIG. 1 to be formed. The second chip stack 30 may also beformed by a similar procedure.

As the description of FIG. 2 also makes clear, the W2W method enablesseveral semiconductor chips formed on each of a plurality of siliconwafers to be stacked in wafer units before dicing, and then electricallyconnected by penetrating electrodes. Therefore, compared to the C2Cmethod where dicing is first performed and then the semiconductor chipsare stacked on a chip-by-chip basis, manufacturing processes can besimplified.

However, the W2W method has a problem that since defective semiconductorchips are included in the stacked wafers in a certain proportion, yielddeteriorates compared to the C2C method. Yield falls cumulatively as thenumber of stacked wafers increases. If yield falls greatly, finalmanufacturing costs become increased compared to those of the C2Cmethod.

FIG. 3A-3C include tables showing the relationship between yield in onewafer (ratio of defective semiconductor chips among the semiconductorchips included in one wafer), number of stacked wafers (number stacked),and yield in the first chip stack 20 or the second chip stack 30.

FIG. 3A shows the relationship between yield in one wafer, number ofwafers stacked, and probability that all of the semiconductor chips inthe first chip stack 20 or the second chip stack 30 are non-defective(all-chip non-defect rate). FIG. 3B shows the relationship between yieldin one wafer, number of wafers stacked, and probability that only one ofthe semiconductor chips in the first chip stack 20 or the second chipstack 30 is defective (one-chip defect rate). FIG. 3C shows therelationship between yield in one wafer, number of wafers stacked, andprobability that two of the semiconductor chips in the first chip stack20 or the second chip stack 30 are defective (two-chip defect rate).

As an example, the case that yield in one wafer is 95% is considered. Inthis case, all-chip non-defect rate of the first chip stack 20 or thesecond chip stack 30 lowers as the number of stacked wafers increases.For example, when the number of stacked wafers is five, the all-chipnon-defect rate of the first chip stack 20 or the second chip stack 30is 77% (=0.95⁵×100). If the number of stacked wafers increases evenmore, the non-defect rate lowers even more.

Moreover, as shown in FIG. 3B, when yield in one wafer is 95%, one-chipdefect rate increases as the number of stacked wafers increases. Forexample, when the number of stacked wafers is five, the one-chip defectrate of the first chip stack 20 or the second chip stack 30 is 20%(=0.95⁴×0.05×5).

Similarly, as shown in FIG. 3C, when yield in one wafer is 95%, two-chipdefect rate increases as the number of stacked wafers increases. Forexample, when the number of stacked wafers is five, the two-chip defectrate of the first chip stack 20 or the second chip stack 30 is 2%.

As the above description makes clear, when the W2W method is employed,as the number of stacked wafers increases, a semiconductor device withlarge memory capacity can be formed with a smaller number of processsteps. On the other hand, the non-defect rate of the first chip stack 20or the second chip stack 30 lowers. Therefore, there is a trade-offrelationship between simplification of the manufacturing method andimprovement of non-defect rate.

Accordingly, the present embodiment aims to achieve both simplificationof the manufacturing method and improvement of non-defect rate byadopting manufacturing processes such as shown in FIG. 4. In the presentembodiment, in the case of finally forming a chip stack including adesired number of (for example, p) non-defective semiconductor chips,rather than stacking p wafers at a time, first, m wafers (m<p) arestacked to form the first chip stack 20 including m semiconductor chips,and, in addition, n wafers (n<p, p≦m+n) are stacked to form the secondchip stack 30 including n semiconductor chips. Then, after identifyingthe number of defective semiconductor chips in these first chip stacks20 (m chips) and second chip stacks 30 (n chips) by a test with atester, the first chip stacks 20 and the second chip stacks 30 aresorted according to the number of defective semiconductor chips includedin the stacks.

Then, the first chip stack 20 and the second chip stack 30 are combinedsuch that the number of non-defective semiconductor chips in the thirdchip stack 40 configured from the first chip stack 20 and the secondchip stack 30 is p. In FIG. 4, description proceeds taking as an examplethe case where m=4, n=5, and p=8. However, the present embodiment is notlimited to these numbers.

Considered herein is the case where m=4, n=5, and p=8, and 500semiconductor chips C are formed in one wafer W. In this case, of the500 first chip stacks (four stacked chips), about 414 are all-chipnon-defect first chip stacks 20 (20(4/4)). Moreover, about 73 areone-chip defect first chip stacks 20 (20(3/4)), about 12 are two-chipdefect first chip stacks 20 (20(2/4)), and about 1 is athree-or-more-chip defect first chip stack 20 (20(1/4)).

In addition, of the 500 second chip stacks 30 (four stacked chips),about 398 are all-chip non-defect second chip stacks 30 (30(5/5)).Moreover, about 82 are one-chip defect second chip stacks 30 (30(4/5)),about 18 are two-chip defect second chip stacks 30 (30(3/5)), and about2 are three-or-more-chip defect first chip stacks 30 (30(2/5)).

In this case, combining first chip stacks 20(4/4) enables a chip stack40′ including eight non-defective chips (zero defective chips) to begenerated. This chip stack 40′ differs from the third chip stack 40 inFIG. 1 and is similar to a conventional chip stack in not including evena single defective memory chip.

Moreover, combining the first chip stack 20(4/4) and the second chipstack 30 (4/5) enables the third chip stack 40 similar to that in FIG. 1including eight non-defective chips (one defective chip) to begenerated.

Alternatively, combining the first chip stack 20(3/4) and the secondchip stack 30(5/5) enables the third chip stack 40 similar to that inFIG. 1 including eight non-defective chips (one defective chip) to begenerated.

In addition, combining the second chip stack 30 (5/5) and the secondchip stack 30(3/5) enables a chip stack 40″ including eightnon-defective chips (two defective chips) to be generated. This chipstack 40″ also includes p=8 non-defective chips, similarly to the thirdchip stack 40.

Note that first chip stacks 20(2/4) and 20(1/4) including two or moredefective chips or second chip stacks 30(2/5) including three or moredefective chips maybe disposed of, or manufactured and sold as low-costproducts of deficient capacity.

As described above, in the present embodiment, when manufacturing asemiconductor device 100 including p non-defective memory chips, thefirst chip stacks 20 including m memory chips and the second chip stacks30 including n memory chips are generated, and these stacks are combinedto manufacture the semiconductor device including p non-defective memorychips. As shown in FIG. 1, such a semiconductor device may be asemiconductor device configured by a chip stack not including even asingle defective memory chip. However, such a semiconductor device mayalso include a semiconductor device configured by the third chip stack40 including one or more defective memory chips. To the extent that thelatter is allowed, a high yield can be achieved. Specifically, wheneight wafers at a time are stacked by the W2W method, yield is 65%, but,as in the above-described example, when the first chip stacks 20 formedby stacking four wafers by the W2W method and the second chip stacks 30formed by stacking five wafers by the W2W method are combined to allowone defective chip, yield can be raised to a maximum of close to 97%(case where manufactured number of first chip stacks 20 and manufacturednumber of second chip stacks 30 are in the ratio of 4:1).

FIG. 5 is a block diagram showing a configuration of a system formanufacturing a semiconductor device according to the presentembodiment. This system comprises a tester 100, a first sorting device200, and a second sorting device 300.

The tester 100 maybe similar to a well-known tester, and identifies aposition and number of defective memory chips included in the first chipstack 20 and the second chip stack 30. The first sorting device 200sorts the first chip stacks 20 and the second chip stacks 30 based onnumbers of defective memory chips obtained by the tester 100. The secondsorting device 300 combines the first chip stacks 20 and the second chipstacks 30 appropriately according to a principle as in FIG. 4 togenerate the semiconductor device 100.

While certain embodiments of the inventions have been described, theseembodiments have been presented by way of example only, and are notintended to limit the scope of the inventions. Indeed, the novel methodsand systems described herein may be embodied in a variety of otherforms; furthermore, various omissions, substitutions and changes in theform of the methods and systems described herein may be made withoutdeparting from the spirit of the inventions. The accompanying claims andtheir equivalents are intended to cover such forms or modifications aswould fall within the scope and spirit of the inventions.

What is claimed is:
 1. A method of manufacturing a semiconductor device,comprising: after stacking m wafers in each of which a plurality ofsemiconductor chips are formed, dicing the m wafers to semiconductorchips to form a first chip stack having m of the semiconductor chipsstacked; after stacking n of the wafers, performing dicing of the nwafers on the basis of the semiconductor chips to form a second chipstack having n of the semiconductor chips stacked; sorting the firstchip stack according to the number of defective semiconductor chipsincluded in the first chip stack; sorting the second chip stackaccording to the number of defective semiconductor chips included in thesecond chip stack; and combining the first chip stack or the second chipstack after sorting to form a third chip stack.
 2. The method ofmanufacturing a semiconductor device according to claim 1, wherein n isa number larger than m by an amount of 1 (n=m+1).
 3. The method ofmanufacturing a semiconductor device according to claim 1, wherein thethird chip stack is formed by combining the first chip stack or thesecond chip stack such that the number of non-defective semiconductorchips included in the third chip stack is p.
 4. The method ofmanufacturing a semiconductor device according to claim 3, wherein n isa number larger than m by an amount of 1 (n=m+1).
 5. The method ofmanufacturing a semiconductor device according to claim 1, furthercomprising: before the dicing, forming a penetrating electrode thatpenetrates the wafers.
 6. The method of manufacturing a semiconductordevice according to claim 1, wherein either one of the first chip stackand the second chip stack includes one defective semiconductor chip, andthe semiconductor chips included in the other of the first chip stackand the second chip stack are all non-defective semiconductor chips. 7.The method of manufacturing a semiconductor device according to claim 6,wherein n is a number larger than m by an amount of 1 (n=m+1).
 8. Themethod of manufacturing a semiconductor device according to claim 6,wherein the third chip stack is formed by combining the first chip stackor the second chip stack such that the number of non-defectivesemiconductor chips included in the third chip stack is p.
 9. The methodof manufacturing a semiconductor device according to claim 1, furthercomprising: before the dicing, forming a penetrating electrode thatpenetrates a wafer.
 10. A semiconductor device, comprising: a first chipstack formed by stacking m wafers in each of which a plurality ofsemiconductor chips are formed, and then dicing the m wafers tosemiconductor chips, the first chip stack comprising a first penetratingelectrode that penetrates m of the stacked semiconductor chips; a secondchip stack formed by stacking n wafers and then dicing the n wafers tosemiconductor chips, the second chip stack comprising a secondpenetrating electrode that penetrates m of the stacked semiconductorchips; and a connecting member that connects the first penetratingelectrode and the second penetrating electrode, a combination of thefirst chip stack and the second chip stack including at least onedefective semiconductor chip.
 11. The semiconductor device according toclaim 10, wherein a distance between the plurality of semiconductorchips included in the first chip stack or a distance between theplurality of semiconductor chips included in the second chip stack issmaller than a distance between two of the semiconductor chips connectedvia the connecting member.
 12. The semiconductor device according toclaim 10, wherein either one of the first chip stack and the second chipstack includes one defective semiconductor chip, and the semiconductorchips included in the other of the first chip stack and the second chipstack are all non-defective semiconductor chips.
 13. The semiconductordevice according to claim 12, wherein a distance between the pluralityof semiconductor chips included in the first chip stack or a distancebetween the plurality of semiconductor chips included in the second chipstack is smaller than a distance between two of the semiconductor chipsconnected via the connecting member.
 14. The semiconductor deviceaccording to claim 10, wherein n is a number larger than m by an amountof 1 (n=m+1).
 15. The semiconductor device according to claim 14,wherein a distance between the plurality of semiconductor chips includedin the first chip stack or a distance between the plurality ofsemiconductor chips included in the second chip stack is smaller than adistance between two of the semiconductor chips connected via theconnecting member.
 16. The semiconductor device according to claim 10,wherein the plurality of semiconductor chips in the first chip stack andthe plurality of semiconductor chips in the second chip stack are joinedby an adhesive agent.
 17. The semiconductor device according to claim10, wherein the defective semiconductor chip is a semiconductor chipdefective in its entirety and not provided for use in its entirety. 18.A management system of a semiconductor device, comprising: a test deviceconfigured to test a first chip stack and a second chip stack, the firstchip stack being formed by stacking m wafers in each of which aplurality of semiconductor chips are formed, and then dicing the mwafers to semiconductor chips, and the second chip stack being formed bystacking n wafers and then dicing the n wafers to semiconductor chips; afirst sorting device configured to sort the first chip stack and thesecond chip stack based on the number of defective semiconductor chipsincluded in the first chip stack and the second chip stack; and a secondsorting device configured to sort the first chip stack and the secondchip stack such that the number of non-defective semiconductor chipsincluded in a combination of the first chip stack and the second chipstack is identical.
 19. The management system of a semiconductor deviceaccording to claim 18, wherein n is a number larger than m by an amountof 1 (n=m+1).
 20. The management system of a semiconductor deviceaccording to claim 16, wherein the first chip stack and the second chipstack are connected by a penetrating electrode before the dicing.